1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device of a large storage capacity. The invention more particularly relates to an arrangement of a memory cell array suitable for higher integration in a dynamic random access memory, and to configuration of peripheral circuitry suitable for the arrangement.
2. Description of the Background Art
FIG. 39 shows a structure of a memory cell of a conventional dynamic random access memory (DRAM). Referring to FIG. 39, a DRAM cell MC includes a capacitor Cm for storing information in a charge form, and an access transistor Tm formed of an n channel MOS transistor responsive to signal potential on a word line WL to connect capacitor Cm to a bit line BL (or /BL).
In a memory cell array, DRAM cells MC are arranged in rows and columns, word line WL is placed corresponding to each row of the memory cells, and a pair of bit lines BL and /BL is placed corresponding to each column of the memory cells. In DRAM cell MC, electric charges corresponding to storage information are accumulated in one electrode node (storage node) SN of capacitor Cm, and a constant voltage Vcp is applied to the other electrode node (cell plate node) CP. Generally, cell plate voltage Vcp is set at a voltage level equal to an amplitude of bit line BL (voltage equal to half a supply voltage Vcc (Vcc/2)).
As shown in FIG. 39, DRAM has a cell MC formed of one transistor and one capacitor (1-transistor/1-capacitor type cell), and it is widely used as a large storage capacity memory such as a main memory of a system since the number of components is small, the occupation area is accordingly reduced and cost per bit is decreased compared with a static random access memory (SRAM) which requires a plurality of transistors for a cell.
FIG. 40 schematically shows an arrangement of memory cells of a conventional DRAM. In FIG. 40, word lines WL0-WL9 and bit lines BL0, /BL0 and BL1, /BL1 are representatively shown.
Referring to FIG. 40, memory cell minimum units MCU each including two memory cells opposite to each other relative to a bit line contact BCT for electrically connecting the memory cells and the bit lines are placed in a row direction and a column direction along a prescribed rule Storage node SN of capacitor Cm of a memory cell (see FIG. 39) is electrically connected to one conductive region of access transistor Tm via a storage node contact SCT. In FIG. 40, a rectangular region AFR is a field region (active region) where the access transistor is formed. Capacitor Cm connected via storage node contact SCT is formed extending over active region AFR to the word lines (stacked capacitor type cell structure).
In the arrangement of memory cells shown in FIG. 40, bit line contacts BCT are formed every other bit line in the row direction. In other words, the memory cells are connected to every other bit line in the row direction (direction in which the word line extends). Bit line contacts BCT of adjacent bit lines are formed at different positions. Bit lines BL0 and /BL0 are arranged in a pair, and bit lines BL1 and /BL1 are arranged in a pair. Accordingly, when one word line is selected, one of the paired bit lines is connected to a memory cell, and the other bit line is not connected to the memory cell.
In the arrangement of memory cells shown in FIG. 40, if the pitch of word lines WL (WL0-WL9) is 2F and the pitch of bit lines (distance between adjacent bit lines) is 2F, memory cell minimum unit MCU occupies an area of 2F.multidot.8F. The occupation area of memory cell minimum unit MCU is larger than that of active region AFR since memory cell capacitor CM extends to the outside of active region AFR. Therefore, the occupation area of a one-bit memory cell region UMR is 2F.multidot.4F=8.multidot.F.sup.2. The occupation area of memory cells can be sufficiently increased in the arrangement in which memory cells are placed alternately in the row and column direction with bit line contact BCT shared between two memory cells.
FIG. 41 shows a circuit which is electrically equivalent to the memory cell arrangement shown in FIG. 40. Referring to FIG. 41, memory cell minimum units MCU are arranged every two word lines in the column direction, and arranged every other bit line in the row direction. Bit lines BL0 and /BL0 are connected to a sense amplifier SAa provided on one side of the memory cell array (region where memory cells are placed), and bit lines BL1 and /BL1 are connected to a sense amplifier SAb placed on the other side of the memory cell array. Sense amplifiers SAa and SAb differentially amplify the potential of corresponding bit lines. Cell plate nodes CP of capacitors Cm included in memory cells MC are commonly connected to a cell plate line CPL and receive cell plate voltage Vcp. Cell plate line CPL is connected commonly to all memory cells MC on the memory cell array.
When one word line is selected, memory cell data is read onto one of each pair of bit lines, and the other bit line in each pair maintains a precharge voltage. If word line WL7 is selected for example, storage data of a memory cell MCa is read onto bit line BL0, and storage data of a memory cell MCb is read onto bit line BL1. On the other hand, there is no memory cell at crossings of bit lines /BL0 and /BL1 and word line WL7, and the bit lines /BL0 and /BL1 keep the precharge voltage level. Sense amplifiers SAa and SAb amplify the potential of bit lines BL0 and BL1 onto which the memory cell data are read using the voltage of the other bit lines /BL0 and /BL1 as a reference voltage, to sense and amplify the storage data.
The paired bit lines are so arranged as to extend in the same direction relative to a corresponding sense amplifier. Such arrangement of the bit lines is referred to as "folded bit line configuration", which provides high noise immunity and easy layout of sense amplifiers.
Specifically, a read bit line onto which storage data of a memory cell is read and a reference bit line providing a reference potential for the read data are arranged to be physically adjacent to each other in the same memory array. As a result, difference in interconnection capacitance of paired bit lines is small and the capacitance of sense nodes of sense amplifiers SAa and SAb is equal so that an accurate sensing operation is achieved.
Further, regarding the sense amplifier, locally generated noises are common mode noises for the paired bit lines to be canceled by a corresponding sense amplifier since the bit lines are arranged to extend in the same direction. Consequently, the noise immunity is increased and accurate sensing and amplifying of memory cell data are possible.
In addition, sense amplifiers SAa and SAb can be arranged alternately on both sides of the bit lines. Accordingly, one sense amplifier may be provided per four bit lines so that the pitch condition of the sense amplifiers is relaxed and the sense amplifiers can be easily arranged even in a highly integrated memory cell array.
In the case of the folded bit line configuration shown in FIGS. 40 and 41, one memory cell is placed per two bit lines in the row direction, and one memory cell is placed per two word lines in the column direction. In other words, one memory cell is arranged per four crossings of word lines and bit lines. A highly integrated DRAM of a large storage capacity is implemented by the micro-lithography. However, the minimum processing dimension of a memory cell for a large storage capacity memory such as the recent 64M bit DRAM and 256M bit DRAM decreases to 0.25 .mu.m or less. Since the required minimum capacitance value of capacitor Cm is determined considering the relation with the bit line load capacitance for transmitting a sufficient read voltage onto a corresponding bit line, miniaturization of a memory cell is limited. Therefore, it is increasingly difficult to arrange memory cells to be highly integrated in a memory cell array using a miniaturization technique.
Memory cells can be arranged in a high density if occupation area per one bit of memory cell can be reduced with the minimum processing dimension unchanged.
FIG. 42 shows an example of a possible arrangement of memory cells. Active region AFR in the array arrangement of memory cells shown in FIG. 42 includes two memory transistors similarly to the arrangement of memory cells shown in FIG. 40. Memory cell minimum unit MCU accordingly includes two memory cells. Active regions AFR are so arranged in the row and column directions as to allow bit line contacts BCT to be aligned in the row direction. In the column direction, memory cell minimum unit MCU is repeatedly placed. Word lines WL0-WL5 are arranged to cross access transistors of active regions AFR. No word line is placed between adjacent memory cell minimum units MC.
According to the array arrangement shown in FIG. 42, bit line contacts BCT are arranged in alignment in the row direction, and active regions AFR are also arranged in alignment in the row direction. Accordingly, memory cells are arranged corresponding to respective crossings of word lines WL (WL0-WL5) and bit lines BL (BL0-BL3). If the pitches of word lines WL and bit lines BL are both 2F, the occupation area of one-bit memory cell region UMR is 6. F2. Consequently, the occupation area of a memory cell of one bit can be decreased by about 25% compared with the folded bit line arrangement shown in FIG. 40, and a highly integrated arrangement of memory cells is achieved to allow more memory cells to be placed in the same array area.
FIG. 43 shows a circuit electrically equivalent to the memory cell arrangement shown in FIG. 42. Referring to FIG. 43, DRAM cells MC are arranged corresponding to respective crossings of word lines WL0-WL5 and bit lines BL0-BL3. Memory cell minimum units MCU are arranged in alignment in the row and column directions. Cell plate nodes of DRAM cells MC are commonly connected to cell plate line CPL to receive cell plate voltage Vcp. When one word line is selected, memory cell data are read onto respective bit lines BL0-BL3. In order to sense and amplify the data of selected memory cells, sense amplifiers SA0-SA3 are arranged corresponding to respective bit lines BL0-BL3. These sense amplifiers SA0-SA3 respectively perform sensing operation using bit lines BL0a-BL3a in the same column of an adjacent memory cell array as bit lines that apply a reference potential.
The configuration where memory cells are arranged corresponding to respective crossings of word lines and bit lines is referred to as "open bit line arrangement." When noises are locally generated in the memory cell array including bit lines BL0-BL3, the noises are not transmitted to the adjacent memory array. As a result, sense amplifiers SA0-SA3 cannot cancel the influence of the noises, and not accurately read data, resulting in a lowered noise immunity.
The sense amplifier generally includes cross-coupled p channel MOS transistors and cross-coupled n channel MOS transistors. In other words, the sense amplifier includes at least 4 MOS transistors as its components. Sense amplifiers SA0-SA3 should be arranged corresponding to respective bit lines BL0-BL3, and the pitch of the sense amplifiers equals to that of the bit lines. As a result, it is difficult to arrange sense amplifiers having a relatively large occupation area (since the pitch of the bit lines becomes extremely small for increasing integration). Therefore, the array arrangement shown in FIGS. 42 and 43 cannot be applied for increase of integration of a large storage capacity memory such as the 64M bit DRAM and 256M bit DRAM.